A Dynamic Random Access Memory (DRAM) is a type of semiconductor arrangement for storing bits of data in separate storage capacitors within an integrated circuit. DRAMs commonly take the form of trench capacitor DRAM cells and stacked capacitor DRAM cells. In the latter, the storage capacitors are formed above read/write transistors. An advanced method of fabricating the latter form, developed by Qimonda, is the buried word line process, which involves the cell transistor gate electrode and word line being built in a trench in an active area (AA) and shallow trench isolation (STI) oxide. The buried word line process uses polysilicon and tungsten (W) wires as the bit lines in an array region (e.g., of the active area) and gate electrode technology in periphery-region transistors (e.g., of the active area).
An advantage of the buried word line technology is that it reduces a contact layer, commonly referred to as the self-aligned contact (SAC) or landing pad contact (LPC), as compared to that of a the normal stacked capacitor DRAM cell.
In existing buried word line processes, the buried word line level is generally processed after active area definition via shallow trench isolation. Then, the bit line contacts are formed, and the needed bit lines are structured. FIG. 1 illustrates an example of an existing buried word line process, which is aimed at fabricating memory cell transistors in the end. Upper and lower portions of each of the series of drawings, FIG. 1A through FIG. 1K, portray respectively top-down and cross-sectional views of a conventional DRAM device 100 fabrication. As shown, DRAM device 100 comprises an array region 101 and a periphery region 102. It is noted that like elements in FIG. 1A through FIG. 1K are given like reference numerals and may not be repeated in every figure for simplicity of description.
In FIG. 1A, an active area definition process is performed where active areas (AA) 110 are defined on a substrate 103 (for example a doped silicon) for both the array region 101 and the periphery region 102 via shallow trench isolation (STI) 111. Next, in FIG. 1B, a trench etching process is performed to form a plurality of buried word line trenches 112 in the substrate 103. Next, in FIG. 1C, a gate oxidation process is performed to form an oxide layer (not shown) on the silicon surface of the trenches 112. This oxide layer may serve/function as the gate dielectric layer for the fabricated memory cell transistor of DRAM device 100. Then, a titanium nitride (TiN) deposition process and a tungsten (W) deposition process are performed to form a TiN layer, or TiN/W layer, or combination thereof, which is denoted as 113, in the formed trenches 112. In particular, it is formed on top of the gate oxide layer. Next, in FIG. 1D, an etching-back process is performed to selectively etch the formed TiN or TiN/W layer or their combination into the trenches 112. In one example, the remainder of the conductive titanium nitride layer 114 in the trenches 112 forms the gate electrode of the fabricated memory cell transistor of DRAM device 100, and the remainder of the conductive TiN/W layer (also denoted as 114) forms the needed word lines. In another example, the remainder of the conductive TiN layer, TiN/W layer or their combination (114) in the trenches 112 forms the gate electrode as well as the needed word line. Next, in FIG. 1E, a cap layer deposition process is performed to form a cap layer 115 which covers the processed surface in FIG. 1D. A chemical mechanical polishing (CMP) process may be performed to planarize the surface of the formed cap layer 115. The cap layer 115 is typically made of dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof. Next, in FIG. 1F, a cap layer removal process is performed to remove the cap layers 115 in the periphery region 102. Next, in FIG. 1G, a periphery gate oxidation process is performed to form a gate oxide layer 150, such as the oxide layers formed in the trenches 112 in FIG. 1C, for the transistors in the periphery region 102.
Next, in FIG. 1H, the bit line contact is patterned on the intended surface of the DRAM device 100 being fabricated by using a mask, and a bit line contact etching process is performed to form bit line contact holes 116 through the cap layer 115. Next, in FIG. 1I, a polysilicon deposition process is performed to form a polysilicon layer 117 covering the processed surface in FIG. 1H, and then a metal deposition process is performed to form a better conducting (metal or metal-based) layer 118 covering the formed polysilicon layer 117. Particularly, polysilicon is deposited into and fills the contact hole 116 formed in FIG. 1H, thereby forming the desired bit line contact plugs 116′. The deposited metal or metal-based material may be titanium (Ti), titanium nitride (TiN), tungsten (W), or any combination thereof. In one example, the metal or metal-based layer 118 is selected to be a titanium nitride/tungsten (TiN/W) layer.
Next, in FIG. 1J, a hardmask layer deposition process is performed for achieving better resolution and profile control of the fabricated DRAM device 100. In one example, the formed hardmask layer 119 also can serve/function as an anti-reflective coating (ARC) layer on top of the metal or metal-based layer 118 formed in FIG. 1I. Finally in FIG. 1K, a bit line mask is applied to pattern the bit lines, and a bit line etching process is performed to form the needed bit lines 120. In some cases, the formed bit line 120 comprises the polysilicon layer 117 and the metal or metal-based layer 118 as well.
In some cases, the formation of the bit line contact may involve performing bit line contact photolithography and etching processes on or around the formed periphery gate oxide 150. For such cases, damage or contamination may be caused to the gate oxide 150 of periphery transistors.
Also, as can be seen in FIG. 1H, the window for etching the cap layer 115 to form the bit line contact hole 116 is quite small, as the cap layer 115 is typically very thin (˜few hundred Å). This may cause additional difficulty for process control of the formation of the intended bit lines.
In addition, an endless desire for a simpler process as well as a simpler device structure has driven the research towards advanced formation methods and structures for the individual components in a stacked DRAM device, such as the word line structure, the bit line structure, the gate structure or the dope region structure, etc.